Universal micro-deformation intermediate-frequency beacon

专利类型：发明专利 

语 言：中文 

申 请 号：CN201510407767.0 

申 请 日：20150713 

发 明 人：王韬沈亦豪蔡莹卓高瞻谢芝茂杨力生曹海林覃大伟徐建 

申 请 人：重庆大学 

申请人地址：400044 重庆市沙坪坝区沙正街174号 

公 开 日：20171103 

公 开 号：CN104977569B 

代 理 人： 

代理机构： 

摘　　要：Abstract：The invention discloses a universal micro-deformation intermediate-frequency beacon, which comprises a clock 1, a clock distributor 2, an FPGA chip 3 and a peripheral circuit thereof, n AD9959 chips 51, 52,..., 5n and n band-pass filter groups 61, 62,..., 6n. The clock 1 provides a reference clock input pin for each AD9959 chip via the clock distributor 2; the FPGA chip 3 comprises a multipath pseudo code generation circuit 31, a multipath sine wave generation circuit 32, a control logic circuit 33 and a serial communication interface circuit 34; the control logic circuit 33 reads a spreading code signal or a sine wave signal, a frequency control word, an amplitude control word and a phase control word are configured for each AD9959 chip via the serial communication interface circuit, and thus two kinds of micro-deformation beacon signals: (1) pseudo code signals which have the same intermediate-frequency carrier and are mutually orthogonal through modulation; and (2) low-frequency sine wave signals which have the same intermediate-frequency carrier and have different frequencies through modulation, are generated. 

主 权 项：一种通用型微变形中频信标机，其特征在于：系统由时钟1、时钟分配器2、FPGA芯片3及其外围电路4、N片AD9959芯片51、52、5N以及N个带通滤波器组61、62、6N等构成。时钟1经时钟分配器2送给每片AD9959芯片的参考时钟输入脚，FPGA芯片3包括多路伪码生成电路31、多路正弦波生成电路32、控制逻辑电路33以及串行通信接口电路34等，控制逻辑电路33读取扩频码信号或者正弦波信号，通过串行通信接口电路配置每片AD9959芯片的频率控制字、幅度控制字、相位控制字，从而生成两种微变形信标机信号：(1)中频载波相同但调制有彼此正交的伪码信号；(2)中频载波相同但调制有不同频率的低频正弦波信号。 

关 键 词： 

法律状态：生效 

IPC专利分类号：G01S7/282